1. Field of the Invention
Generally, the present disclosure relates to semiconductor devices, such as integrated circuits, in which, in addition to active circuit elements, such as transistors and the like, passive circuit elements, and in particular capacitors, also have to be provided in view of superior device performance and/or extending device functionality, for instance, RF applications and the like.
2. Description of the Related Art
Continuous progress has been made in the semiconductor industry, thereby now providing integrated circuits having incorporated therein a very large number of circuit elements, such as transistors and the like. In addition to the transistor elements, which are typically provided in the form of digital switches and/or analog components for controlling voltage and/or currents within the semiconductor device, there is an ongoing development to integrate additional functionality into a single semiconductor device, thereby forming even complete systems on a single chip (SoC). Consequently, passive circuit elements, such as inductors, capacitors and the like, have to be implemented in an increasing number of integrated circuits, in addition to the typically used resistors and capacitors for decoupling and information storage purposes.
For example, many manufacturing strategies have been developed for incorporating capacitive structures into the design of complex integrated circuits, for instance, serving as decoupling capacitors, intended for stabilizing, for instance, the operating voltage, in particular in critical device areas, in which fast switching transistor elements may cause moderately high transient currents. To this end, semiconductor-based capacitor structures, for instance, having one electrode in the active semiconductor material, may be provided at strategically appropriate locations in the semiconductor device so as to reduce supply voltage fluctuations. In other cases, a plurality of capacitors has to be incorporated in order to realize storage areas, such as dynamic RAM areas. In these storage areas, a bit of information is typically stored by using one capacitor and an associated transistor, wherein, in view of achieving a high bit density, the capacitors may typically be provided as deep trench capacitors, which, however, may require additional complex process steps for forming a deep trench and appropriately filling the trench with the conductive and dielectric materials.
When providing capacitive structures in the “device” level of a semiconductor device, i.e., in and on the semiconductor material, which is also used for forming the active circuit elements, such as sophisticated transistors for logic areas in silicon-based integrated circuits relying, for instance, on the well-established CMOS technique, these structures are preferably implemented as NMOS capacitors due to their superior characteristics, for instance, with respect to capacitance/area ratio, frequency response for moderately high frequencies and the like. As a consequence, NMOS capacitors in CMOS integrated circuits have become widely adopted device architecture and, therefore, these NMOS capacitors represent the “standard” capacitor type at device level. For this reason, many appropriate process strategies have been developed and are available for forming such NMOS capacitors along with transistors in the device level.
In recent developments of semiconductor production, not only the critical dimensions of circuit elements, such as the gate length of transistors and the like, have been continuously shrunk, thereby presently arriving at a gate length of 30 nm and significantly less for planar transistor configurations, but also reduced power consumption and increased functionality have been addressed. For example, for time critical signal paths in an integrated circuit, complex gate electrode structures based on high-k dielectric materials in combination with metal-containing electrode materials may frequently be used, thereby reducing, among other things, static gate leakage, while still providing a very low oxide equivalent thickness of the gate dielectric, which is necessary for proper static gate control. In less time critical circuit areas, typically, transistor elements with increased thickness of the gate dielectric material in combination with moderately high supply voltages are used in the device design.
In addition to the general quest for reducing overall power consumption while still maintaining high performance of integrated circuits, there is also an increasing demand for implementing passive circuit areas of increased functionality, for instance, by incorporating RF components, which, in turn, may impart superior connectivity functionality to an integrated circuit. Therefore, increasingly, inductive and capacitive structures are incorporated into the design of integrated circuits, wherein certain requirements are to be met, in particular by the capacitors, with respect to functionality, stability and the like. For instance, in many applications, a capacitor is required to allow operation on the basis of a voltage with alternate polarity, thereby imposing certain constraints on the overall design of the capacitive structure. For example, it is well known that, for a capacitor, such as an NMOS capacitor, formed in the active semiconductor material, for instance, by using appropriately dimensioned and composed “gate electrode structures” including a gate dielectric material as a capacitor dielectric, the resulting capacitance will depend, on the one hand, on the capacitance determined by the distance between the capacitor “plates.” Here, the gate electrode material is one electrode of the capacitor and the semiconductor material acts as the second capacitor electrode, wherein these electrodes are separated by the gate dielectric material, which, therefore, defines, at a first glance, the distance of the electrodes. Moreover, the dielectric characteristics of the dielectric material are a further factor determining the capacitance. Despite these structurally determined influences, the capacitance will, on the other hand, significantly vary with the voltage applied to the “gate” electrode structure. That is, similar to the typical transistor functionality, the gate voltage controls the charge carrier distribution in the capacitor body, which is basically a transistor body with appropriately selected lateral dimensions, and, therefore, the effective capacitance of the capacitor is significantly affected by the gate voltage.
With reference to FIGS. 1-3, a typical prior art NMOS capacitor will now be described that is formed on the basis of conventional design concepts so as to provide a capacitive structure in the device level of a semiconductor device.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100, which, as previously discussed, may comprise a plurality of circuit elements, such as transistors and the like, which, for convenience, are not illustrated in FIG. 1. In addition to these non-depicted circuit elements, the device 100 comprises a capacitive structure 150 that is formed in and on a semiconductor material 101, which is typically provided as a silicon substrate. In accordance with typical standards in the semiconductor industry, the substrate 101 may represent a P-doped substrate material. It should be appreciated that the substrate 101 may extend along a depth direction, i.e., in FIG. 1, a vertical direction pointing to the bottom of FIG. 1, so as to have a thickness of, for instance, several hundred micrometers.
An isolation structure 102, such as a trench isolation structure, for example, a shallow trench isolation (STI), is formed in a surface layer of the substrate 101 and thus laterally defines the dimensions of the capacitive structure 150 in accordance with overall design requirements. The isolation structure 102 may also be provided in the form of a locally oxidized isolation region, depending on the overall process strategies used for forming the semiconductor device 100. A vertical extension of the isolation structure 102 into the depth of the substrate 101 may depend on the process strategy used. Within the area laterally defined by the isolation structure 102, there is provided an N-doped semiconductor region 103, which may also be referred to as an N-well. The semiconductor region 103 may, therefore, typically have a dopant profile similar to any other circuit elements, such as transistors, which require an N-well doping. As discussed above, N-well capacitors have become a preferred option for capacitive structures that are formed based on a semiconductor material due to superior characteristics in terms of frequency response and generally increased capacitance/area ratio.
Moreover, in the semiconductor region 103, are an appropriate number of highly doped semiconductor regions, which may also be referred to as contact structures, individually indicated by contact structures 110A, 110B and 110C or commonly indicated as contact structures 110. The contact structures 110 may comprise an appropriate contact metal, which is indicated in FIG. 1 as 112A, 112B, 112C and which is connected to a contact pad or terminal, here symbolically represented by a line 114. It should be appreciated that, except for the highly doped semiconductor regions 111A, 111B, 111C (collectively referred to as highly doped semiconductor regions 111), any other components of the contact structures 110A, 110B, 110C are to be understood as symbolic representations, which do not reflect the actual implementation. For example, respective metal-containing regions may be formed so as to be in contact with the highly doped semiconductor regions 111 based on well-established contact regimes, as are also to be applied for any other circuit elements, such as transistors and the like.
Moreover, electrode structures 120A, 120B (collectively referred to as electrode structures 120) are formed on the basis of materials and process strategies which are also compatible with the manufacturing process for forming gate electrode structures of transistor elements. That is, except for the lateral dimensions, the electrode structures 120 may basically have the same configuration as any gate electrode structures, including a dielectric layer 123, which is formed on the semiconductor region 103 and which represents the dielectric material of the capacitive structure 150. Depending on the degree of sophistication of the semiconductor device 100, the dielectric layer 123 may be comprised of dielectric materials, such as silicon dioxide, silicon nitride, silicon oxynitride, high-k dielectric materials, or any combination thereof. Similarly, the physical thickness and the equivalent oxide thickness may basically correspond to the analogous characteristics of gate electrode structures for at least one type of transistors to be provided in the semiconductor device 100. Also, an electrode material 121A, 121B, which may represent any appropriate conductive material that is compatible with the overall design and process strategy of the device 100 is formed on the dielectric material 123 in combination with an appropriate sidewall spacer structure 122A, 122B. The electrode structures 120, when appropriately electrically connected to each other by any appropriate interconnection regime, schematically indicated by a line 124, may thus represent one electrode of the capacitive structure 150. With respect to the material composition of the electrode materials 121A, 121B, it is to be noted that, also in this case, a configuration is typically used that is compatible with at least one type of transistor gate electrodes, and, therefore, highly doped polysilicon, amorphous silicon, metal-containing work function metals and metal-containing material layers may be implemented in the electrode materials 121A, 121B, depending on the overall process and device requirements.
Upon operating the capacitive structure 150, a voltage may be applied between the electrode structures 120 and the substrate 101, which is typically at ground potential, thereby forming a second electrode structure of the capacitive structure 150. Consequently, for a given voltage, that is, for a given “gate” voltage, the charge carrier distribution in the region 103 will depend on this voltage. Since one contribution to the resulting capacitance of the structure 150 is the charge carrier distribution, such as width of a space charge region, presence of a conductive channel at the interface and the like, and a further contribution stems from constructive criteria, i.e., the thickness and type of the dielectric layer 123 and the lateral dimensions thereof, a pronounced dependency of the effective capacitance on the applied voltage is observed. Consequently, for a substantially constant voltage applied across the capacitive structure 150, a substantially constant capacitance may be obtained. As discussed above, preferably in the industry, an N-well capacitive structure is used due to the increased capacitance/area ratio compared to P-well based capacitors. In the example illustrated in FIG. 1, a “depletion-type” structure is presented, wherein the highly doped regions 111 and the N-well region 103 have the same conductivity type.
As discussed above, there is an increasing demand for capacitors in semiconductor devices, which have to provide a substantially constant capacitance over a certain range of voltages applied to the capacitor. For example, implementing a more or less complete system on a single chip with RF functionality may require capacitors that have to operate at varying voltages or even at voltages of alternate polarity, which renders the capacitive structure 150 less than desirable for the following reasons.
FIG. 2 illustrates a graph 200 that depicts the progression of the capacitance of the capacitive structure 150 for a varying “gate” voltage, i.e., a voltage applied to the line 124, connecting the “gate” electrode structures and a terminal connected to the substrate 101. In FIG. 2, a range of voltages 201 is shown, for which it is desired to have a substantially constant capacitance. On the other hand, curve 202 illustrates qualitatively the variation of the capacitance within the range 201. In the present example, a required width of the range 201 corresponds to −3.3 to +3.3V. As is evident from FIG. 2, the capacitance for the structure 150 as shown in FIG. 1 has a moderately high capacitance at a voltage of 3.3V and higher due to charge carrier accumulation in the vicinity of the dielectric layer 123. For zero voltage, however, a significant drop of the capacitance may be observed, which may result in a minimum capacitance at the voltage of −3.3 V and less, which in total may result in a drop of more than 50% across the desired voltage range 201. Since such a significant variation of the capacitance is considered inappropriate for applications requiring a substantially constant capacitance, alternative approaches have been applied.
To this end, frequently, capacitive structures may be implemented in the metallization system of the semiconductor device 100 (not shown), which typically comprises a plurality of metallization layers including conductive lines, such as aluminum lines, copper lines and the like, which are separated by an appropriate dielectric material in each layer. Moreover, the individual layers of the plurality of stacked metallization layers are typically connected by so-called vias, which are also embedded in an appropriate dielectric material, thereby enabling a highly complex wiring system for connecting the circuit elements in the device level with contact pads, which may finally be used for connecting the semiconductor device 100 with the periphery. Typically, capacitive structures provided in the metallization system have to be formed by interdigitized metal lines for both capacitor electrodes, thereby requiring a specific connection regime between the individual electrode fingers and the plurality of metallization layers across which the respective capacitive structure is distributed. As a consequence, complex processing may be required and, in particular, a complex metallization system has to be provided in order to implement the capacitive structure that allows a voltage-independent operation of the capacitor and in particular offers the potential for using alternate polarity voltages. Moreover, positioning of respective capacitive structures that are formed in the metallization system is restricted to specific areas within the metallization system and thus reduces design flexibility. That is, typically, vertical offset and horizontal offset of the position of such capacitors is required with respect to a desired design position in the device level, which may unduly affect the overall efficiency of the capacitor.
On the other hand, shifting the working point of the capacitive structure 150 so as to obtain a substantially flat behavior of the capacitance across the desired voltage range is not a desirable option, as will be discussed with reference to FIG. 3.
FIG. 3 illustrates a graph 300, in which curve 302B substantially corresponds to the curve 202 of FIG. 2, while curve 302A represents the dependency of the capacitance on the voltage after biasing the contact structures 110, i.e., the line 114 (see FIG. 1). It appears that one would obtain the desired substantially flat capacitance/voltage behavior. However, applying such a regime to the capacitive structure 150 would lead to a biasing of the respective PN junction between the region 103 and the substrate 101, which is still on ground potential. As a consequence, due to driving the PN junction into or near the conductive state renders this option less than desirable due to pronounced leakage.
In view of the situation described above, the present disclosure therefore relates to techniques in which a capacitive structure may exhibit desired capacitance/voltage behavior with significantly reduced variation, thereby avoiding or at least reducing the effects of one or more of the problems identified above.